1. Field of the Invention
The invention relates to a semiconductor integrated circuit, and particularly to an accurate comparator circuit preventing deterioration of a voltage comparison accuracy.
2. Description of the Background Art
In recent years, analog/digital-mixed integrated circuits that have analog circuits integrated in digital integrated circuits of a CMOS (Complementary Metal Oxide Semiconductor) process have been increasingly employed, and analog-to-digital converter (ADC) circuits serving as interfaces for connection between the analog and digital circuits have increased in importance. The ADC circuits can be classified under various types such as a successive approximation type, a pipeline type, a flash type, a ΣΔ type and a dual integration type. In any one of these types, a voltage comparing operation is required, and a comparator circuit is essential. There is a tendency to increase a resolution of the ADC circuit incorporated into a CMOS analog/digital mixed integrated circuit such as a sensor. This increases a necessity for employing a comparator circuit having a high voltage comparison accuracy.
For example, Japanese Patent Laying-Open Nos. 2001-189633 (Patent Document 1) and 11-150454 (Patent Document 2) as well as PCT National Publication No. 09-512684 (Patent Document 3) have disclosed comparator circuits used in analog-to-digital converter circuits and the like.
The comparator circuit disclosed in the Patent Document 1 is of an OOS (Output Offset Storage) type. The OOS type of comparator circuit includes an amplifier circuit, a latch circuit and a capacitor. This OOS type of comparator circuit performs an correcting operation on an offset voltage of the amplifier circuit before a voltage comparing operation. More specifically, two capacitors connected to respective differential outputs of the amplifier circuit accumulate charges corresponding to a value obtained by multiplying the offset voltage of the amplifier circuit by a gain of the amplifier circuit.
In the voltage comparing operation, two input voltages to be compared are applied to the amplifier circuit. The amplifier circuit amplifies the two input voltages, and outputs them. In this operation, the two capacitors cancel the offset voltage in the output voltages of the amplifier circuit, and the voltages not including the offset voltage can be obtained. The output voltage of the amplifier circuit is provided to the latch, which converts it into a logic level of H- or L-level, and outputs it as a result of the comparison.
In the comparator circuit disclosed in the Patent Document 1, no problem arises when the comparator circuit receives the comparison target voltages of a minute voltage difference. However, when the comparator circuit receives the comparison target voltages of a large voltage difference, the voltages held by the two capacitors lower, and the accuracy of the offset voltage correction deteriorates.